Tubagus Dafa
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PROJECTEMBEDDED SYSTEMS

F1 Race Game

Role: Embedded Systems Engineer

Timeline: 2026-05 — 2026-05

Org: University of Indonesia - Engineering Undergraduate

Context

Engineered the F1 Race Game (Reaction Time & Reflex Tester), a high-precision biometric instrument designed to evaluate human reflex latency in milliseconds. Developed to mitigate the inherent processing latency of high-level operating systems, the entire firmware architecture was authored strictly in AVR Assembly to achieve absolute control over the ATmega328P hardware registers and instruction overhead.

Hardware Architecture

  • Microcontroller Unit (MCU): Arduino UNO R3 (ATmega328P).
  • Input Interface: Dual Push Buttons utilizing internal pull-up resistors connected to PD2 and PD3.
  • Output Actuation: Sequenced LED array (PD4-PD7, PB0) and an Active Buzzer.
  • Display Interface: LCD 16x2 driven via an I2C Expander (PCF8574) on analog pins SDA/SCL.

Low-Level Software Implementation & Algorithms

The system integrated 7 core microcontroller modules utilizing pure Assembly instructions:

  • Timer/Counter (High-Precision Measurement): Configured Timer 1 in Normal Mode. The elapsed time from visual stimulus to human physical reaction was captured by reading the 16-bit TCNT1 register.
  • Arithmetic Module (16-bit Division): Because the AVR architecture lacks a hardware division instruction, I engineered a custom 16-bit software division subroutine (div16_by8) utilizing shift-and-subtract bitwise manipulation to convert raw hardware ticks into precise millisecond strings.
  • Input Detection Architecture: Purposefully bypassed standard External Interrupts (INT0/INT1) in favor of high-speed Polling loops utilizing the SBIS instruction. This architecture effectively handled hardware debouncing and robustly managed "False Start" violation logic without unwanted state transition anomalies.
  • Random Seed Generation (ADC & LFSR): Implemented a Linear-Feedback Shift Register (LFSR) algorithm to generate randomized visual delays. The initial seed was dynamically extracted by reading analog electrical noise from a floating ADC pin (A0).
  • Non-Volatile Storage (EEPROM): Engineered direct register manipulation (enabling EEMPE master lock bits) to safely read, compare, and permanently write High Score data to the EEPROM without memory corruption.
  • Communication Protocols:
    • Authored a raw bit-banging implementation of the I2C Protocol to transmit ASCII data to the LCD display.
    • Configured USART Serial Communication to asynchronously stream real-time data logs to a PC at a 115200 baud rate.

Associated Entities

  • Competencies: Embedded Systems, AVR Assembly, ATmega328P, Hardware Architecture, I2C Protocol, Digital Arithmetic