FAST (Flood Alert SysTem)

Built FAST (Flood Alert SysTem), a real-time hardware flood detection and early warning prototype. Developed as a capstone team project for the Digital System Design curriculum, the system mitigated the latency and unreliability of manual flood monitoring. It automatically detected critical water levels and instantly triggered visual and auditory alerts. The prototype operated entirely on discrete digital logic ICs — demonstrating fundamental digital system design without programmable abstraction.

Hardware Architecture & BOM

The physical prototype was assembled across four linked breadboards, comprising the following components:

• Sensing & Conversion: Analog Water Sensor, LM339 Voltage Comparator, 1kΩ & 10kΩ Potentiometers.
• Logic & Sequential ICs: 74HC02 (Quad 2-Input NOR Gate), 74192 (Synchronous Up/Down Decade Counter), 74247 (BCD to 7-Segment Decoder).
• Output & Actuation: Common-Anode 7-Segment Display, BC547 NPN Transistor, 5V Active Buzzer, LED Output Array (Red, Green, Blue).

Digital Logic Implementation & Signal Flow

Designed a deterministic signal processing pipeline converting an analog environmental input into discrete digital logic states:

1. Analog-to-Digital Thresholding: The analog water sensor outputs a variable voltage relative to water immersion. The LM339 Comparator evaluates this against a manual reference threshold set by a 10kΩ Potentiometer. Upon exceeding the critical threshold, it transitions to a discrete HIGH output.
2. State Memory (SR Latch): The comparator's signal triggers a custom-built SR Latch implemented entirely from 74HC02 NOR gates. This ensures the critical alarm state is retained even if water levels fluctuate rapidly (permanently latching the Red LED and engaging a BC547 transistor to drive the auditory buzzer). A physical push-button serves as the reset pin, clearing the latch manually.
3. Event Tracking (Sequential Logic): The initial HIGH pulse from the comparator is routed to the clock input of the 74192 Counter, incrementing the system's cumulative count of discrete flood events.
4. Data Visualization: The binary output from the decade counter is decoded by the 74247 to drive a 7-segment display, providing a running count of detected flood events.

Core Competencies

Digital System Design, Discrete Logic Gates, Circuit Prototyping, Analog-to-Digital Conversion